This project has received funding from the EUís Horizon 2020 programme for research, technological development and demonstration under grant agreement no 644905.

Publications

Deliverables

D1.1 Status on modelling, fault/reconfiguration modelling and reliability metrics
D1.2 Cross-layer CPS modelling framework
D1.3 Fault models and reliability metrics
D1.4 Reconfiguration modelling
D2.1 Verification, debugging and testing methods
D2.2 Verification, debugging and testing tools
D2.3 Fault management infrastructure verification tools
D3.1 Dynamic, semi-formal and formal reliability analysis methods
D3.2 Dynamic, semi-formal and formal reliability analysis tools
D3.3 System-level reliability analysis tools
D4.1 Status on fault management
D4.2 Online fault detection mechanisms
D4.3 FDIR schemes (incl. reconfiguration, health map, fault classification)
D4.4 CPS run-time for SW task deployment
D5.1 Integrated demonstrator on modelling, verification and reliability analysis
D5.2 Integrated FPGA demonstrator of the fault management framework
D5.3 Silicon demonstrator for fault management and mixed-signal reliability verification
D6.1 Market analysis
D6.2 Joint and individual Technology Exploitation Plans
D6.3 Dissemination and Communication strategy
D6.4 IMMORTAL Website and factsheet
D6.5 Dissemination and communication report;

Technical Papers

2017

- Jan Malburg, Tino Flenker, Görschwin Fey (DLR), "Property Mining using Dynamic Dependency Graphs", Asia and South Pacific Design Automation Conference (ASP-DAC), January 2017. (free access)

- Heinz Riener, Rüdiger Ehlers, Görschwin Fey (DLR), "CEGAR-based EF Synthesis of Boolean Functions with an Application to Circuit Rectification", Asia and South Pacific Design Automation Conference (ASP-DAC’17), 2017. (free access)

- Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Nevin George, Adeboye Stephen Oyeniran,  Tsotne Putkaradze,   Apneet Kaur,  Jaan Raik, Gert Jervan, Raimund Ubar, Thomas Hollstein (Tallinn UT), From Online Fault Detection to Fault Management in NoC Routers: A Ground-up Approach, DDECS 2017.

- Siavoosh Payandeh Azad, Behrad Niazmand, Apneet Kaur Sandhu, Jaan Raik,  Gert Jervan, Thomas Hollstein (Tallinn UT), Automated Area and Coverage Optimization of Minimal Latency Checkers, IEEE European Test Symposium, ETS 2017.

- Siavoosh Payandeh Azad, Behrad Niazmand,  Karl Janson, Thilo Kogge, Jaan Raik,  Gert Jervan, Thomas Hollstein (Tallinn UT), Comprehensive Performance and Robustness Analysis of 2D Turn Models for Network-on-Chips, ISCAS 2017.

Heinz Riener, Ruediger Ehlers, and Goerschwin Fey (DLR),  "Counterexample-Guided EF Synthesis of Boolean Functions", In ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Bremen, Germany, 2017. (free access)

- Tino Flenker and Goerschwin Fey (DLR), "Mapping Abstract and Concrete Hardware Models for Design Understanding", In IEEE Int’l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Dresden, Germany, 2017. (free access)

- Heinz Riener and Goerschwin Fey (DLR), "Computing Exact Fault Candidates Incrementally", 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe), Lausanne, Switzerland, 2017. (free access)

- Jan Malburg, Heinz Riener, Goerschwin Fey (DLR) "Mining Latency Guarantees for RT-level Designs", 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe), Lausanne, Switzerland, 2017. (free access)

2016

- Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon Ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao (All IMMORTAL partners), Designing Reliable Cyber-Physical Systems, Forum on specification & Design Languages (FDL'16), Bremen, Germany, 2016. (free access)

- Jan Malburg, Alexander Finder, Görschwin Fey (DLR) „Debugging Hardware Designs Using Dynamic Dependency Graphs”, Journal of Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Volume 47 Issue PB, November 2016, Pages 347-359, Elsevier Science Publishers, doi:10.1016/j.micpro.2016.10.004. (free access)

- Alt, J. and Bernardi, P. and Bosio, A. and Cantoro, R. and Kerkhoff, H.G. and Leininger, A and Molzer, W. and Motta, A. and Pacha, C. and Pagani, A and Rohani, A. and Strasser, S. (U.Twente) Thermal issues in test: An overview of the significant aspects and industrial practice. (Invited) In: IEEE 34th VLSI Test Symposium (VTS 2016), 25-27 Apr 2016, Las Vegas, NV, USA. pp. 1-4. IEEE. ISBN 978-1-4673-8454-4

- Ibrahim, A.M.Y. and Kerkhoff, H.G. (U.Twente) Analysis and design of an on-chip retargeting engine for IEEE 1687 networks. In: 21st IEEE European Test Symposium (ETS 2016), 23-26 May 2016, Amsterdam, The Netherlands. pp. 1-6. IEEE Circuits & Systems Society. ISBN 978-1-4673-9659-2

- Ibrahim, A.M.Y. and Kerkhoff, H.G. (U.Twente) Efficient Utilization of Hierarchical iJTAG Networks for Interrupts Management. In: 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 19-20 Sept 2016, Storrs, CT, USA. pp. 97-102. IEEE Computer Society. ISBN 978-1-5090-3623-3

- Ibrahim, A.M.Y. and Kerkhoff, H.G. (U.Twente) Towards an automated and reusable in-field self-test solution for MPSoCs. In: 28th International Conference on Microelectronics (ICM 2016), 17-20 Dec 2016, Giza, Egypt. pp. 249-252. IEEE Computer Society. ISBN 978-1-5090-5721-4

- Sandip Ray, Ian G. Harris, Goerschwin Fey, Mathias Soeken (DLR): Multilevel Design Understanding: From Specification to Logic, IEEE ICCAD, 2016.

Eli Arbel, Barak Erez, Bodo Hoppe, Udo Krautz, Shlomit Koyfman and Shiri Moran (IBM), "Gating Aware Error injection", Haifa Verification Conference HVC 2016.

- Niklas Krafczyk, Heinz Riener, Görschwin Fey (DLR), "WCET for Software in the Context of Cyber-Physical Systems", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'16), 2016. (free access)

- Heinz Riener, Görschwin Fey (DLR), "Exact Diagnosis using Boolean Satisfiability", International Conference on Computer Aided Design (ICCAD'16), 2016. (free access)

-Zambrano Constantini, A.C. and Kerkhoff, H.G. (U.Twente) Determination of the drift of the maximum angle error in AMR sensors due to aging. In: 2016 IEEE 21st International Mixed-Signal Testing Workshop (IMSTW), 4-6 July 2016, Sant Feliu de Guíxols, Spain. pp. 92-96. IEEE. ISBN 978-1-5090-2751-4

- Zambrano Constantini, A.C. and Kerkhoff, H.G. (U.Twente) Online digital compensation method for AMR sensors. In: IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, 26-28 Sept 2016, Tallinn, Estonia. IEEE . ISBN 978-1-5090-3561-8

- Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik, Gert Jervan, Thomas Hollstein (Tallinn UT): "Holistic Approach for Fault-Tolerant Network-on-Chip based Many-Core Systems",2nd International Workshop on Dynamic Resource Allocation and Management in Embedded, High Performance and Cloud Computing DREAMCloud 2016 (arXiv:cs/1601.04675), DREAMCloud/2016/05

- Behrad Niazmand, Siavoosh Payandeh Azad, José Flich, Jaan Raik, Gert Jervan, Thomas Hollstein (Tallinn UT), "Logic-Based Implementation of Fault-Tolerant Routing in 3D Network-on-Chips", NOCS 2016, Nara, Japan.

- Siavoosh Payandeh Azad, Behrad Niazmand, Peeter Ellervee, Jaan Raik, Gert Jervan, Thomas Hollstein (Tallinn UT), "SoCDep²: A framework for dependable task deployment on many-core systems under mixed-criticality constraints", ReCoSoC 2016.

- Bernhard Aichernig, Roderick Bloem, Franz Pernkopf, Franz Röck, Tobias Schrank and Martin Tappler (TU Graz), Poster: "Learning Models of a Network Protocol using Neural Network Language Models" at the S&P 2016

- Roderick Bloem, Robert Könighofer, Ingo Pill, Franz Röck (TU Graz), "Synthesizing Adaptive Test Strategies from Temporal Logic Specifications", FMCAD, 2016.

- Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler and Goerschwin Fey (DLR), "metaSMT: Focus On Your Application And Not On Solver Integration", International Journal of Software Tools for Technology Transfer (STTT), 2016. (free access)

- Heinz Riener and Goerschwin Fey (DLR), "Counterexample-Guided Diagnosis", International Verification and Security Workshop (IVSW), 2016. (free access)

- Jenihhin, Maksim; Squillero, Giovanni; Copetti, Thiago Santos; Tihhomirov, Valentin; Kostin, Sergei; Gaudesi, Marco; Vargas, Fabian; Raik, Jaan; Sonza Reorda, Matteo; Bolzani Poehls, Leticia; Ubar, Raimund; Medeiros, Guilherme Cardoso (Tallinn UT). Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits. Journal of Electronic Testing-Theory and Applications (JETTA), Springer, 1−17, June 2016. (url

- Karputkin, Anton; Raik, Jaan (Tallinn UT). A Synthesis-Agnostic Behavioral Fault Model for High Gate-Level Fault Coverage. In: ACM/IEEE Design, Automation & Test in Europe Conference (DATE), pp. 1124-1127), 2016. (url)

 - Copetti, Thiago; Medeiros, Guilherme; Poehls, Leticia; Vargas, Fabian; Kostin, Sergei; Jenihhin, Maksim; Raik, Jaan (Tallinn UT). Gate-Level Modelling of NBTI-Induced Delays Under Process Variations. 17th IEEE Latin-American Test Symposium (LATS 2016), Foz do Iguaçu, Brazil, 6th - 8th April 2016. IEEE Computer Society Press, 75−80.

- K. Shibin, S. Devadze, A. Jutman (Testonica Lab), “On-line Fault Classification and Handling in IEEE1687 based Fault Management System for Complex SoCs” in Proc. 17th IEEE Latin-American Test Symposium (LATS’2016), Foz do Iguaçu, Brazil, April 6-8, 2016, pp. 1-6.

- J. Wan, H.G. Kerkhoff and J. Bisschop (U.Twente), “Simulating NBTI Degradation in Arbitrary Stressed Analog/Mixed-Signal Environments”, IEEE Transactions on Nanotechnology, Issue 2, pp. 137-148, March 2016.

- A. Zambrano (U.Twente), “On-line Monitoring of Maximum Angle Error in AMR Sensors”, International Symposium On-Line Testing Symposium (IOLTS), Catalunya, Spain, July 2016.

- G. Ali , A. Badewy and H.G. Kerkhoff (U.Twente), “Online Management of Temperature Health Monitors using the IEEE 1687 Standard”, TESTA Workshop (ETS), Amsterdam, The Netherlands, May 2016. 

- Niels Thole, Lorena Anghel, and Goerschwin Fey (DLR), "A hybrid algorithm to conservatively check the robustness of circuits",  In IEEE European Test Symposium (ETS), Amsterdam, The Netherlands, May 2016.

- Zhao, Yong and Kerkhoff, H.G. (U.Twente) A genetic algorithm based remaining lifetime prediction for a VLIW processor employing path delay and IDDX testing. In: International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2016 , 12-14 Apr 2016, Istanbul, Turkey. pp. 10-14. IEEE Computer Society. ISBN 978-1-5090-0336-5

- Ali, G. and Badawy, A. and Kerkhoff, H.G. (U.Twente) Accessing on-chip temperature health monitors using the IEEE 1687 standard. In: 23rd IEEE International Conference on Electronics, Circuits and Systems (ICECS), 11-14 Dec 2016, Monte Carlo, Monaco. pp. 776-779. IEEE Circuits & Systems Society. ISBN 978-1-5090-6113-6

- A. Jutman, K. Shibin, S. Devadze (Testonica Lab), “Reliable Health Monitoring and Fault Management Infrastructure based on Embedded Instrumentation and IEEE 1687,” in Proc. of AUTOTESTCON’2016, Anaheim, USA, Sept 12-15, 2016, pp. 240-249.

- A. Jutman, S. Devadze, K. Shibin (Testonica Lab), “Synchronization, Calibration and Triggering of IEEE 1687 Embedded Instruments”, in Proc. of the 17th Workshop on RTL and High Level Testing (WRTLT’2016), Nov. 24-25, 2016, Hiroshima, Japan, pp. 1-6.

- Tino Flenker and Goerschwin Fey (DLR), "Matching abstract and concrete hardware models for design understanding", In Workshop on Design Automation for Understanding Hardware Designs (DUHDe'16) (free access)

- Heinz Riener, Robert Könighofer, Görschwin Fey, and Roderick Bloem (DLR, TU Graz), "SMT-Based CPS Parameter Synthesis", in Applied Verification for Continuous and Hybrid Systems (ARCH'16), Vienna, Austria, April 11, 2016 (free access)

2015

- Saltarelli, P.; Niazmand, B.; Raik, J.; Hariharan, R.; Govind, V.; Hollstein, T.; Jervan, G. (Tallinn UT), A framework for combining concurrent checking and on-line embedded test for low-latency fault detection in NoC routers. 9th ACM International Symposium on Networks-on-Chip (NOCS) 2015. (url, free access)

- Saltarelli, P.; Niazmand, B.; Raik, J.; Hariharan, R.; Jervan, G.; Holistein, T. (Tallinn UT), A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers. IEEE Euromicro Conference on Digital System Design (DSD) 2015, 288-292. (url, free access)

- Saltarelli, P.; Niazmand, B.; Hariharan, R.; Raik, J.; Jervan, G.; Hollstein, T. (Tallinn UT), Automated Minimization of Concurrent Online Checkers for Network-on-Chips. 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015). (url, free access)

Open Data (NoC router (LBDR+arbiter), verification environment) download

- Jaan Raik (Tallinn UT ), "Immortalizing Many-Core Systems: Early Experiences of the Horizon 2020 Action IMMORTAL", at the 7th International Workshop on Dependable Many-Core Computing (DMCC) in Amsterdam, July 23, 2015. (url, free access)

- Jasnetski, Artjom; Raik, Jaan; Tsertov, Anton; Ubar, Raimund (Tallinn UT). New Fault Models and Self-Test Generation for Microprocessors using High-Level Decision Diagrams. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems - DDECS. Belgrade, Serbia, April 22-24, 2015. (url)

- Roderick Bloem, Rüdiger Ehlers, Robert Könighofer (TU Graz), "Cooperative Reactive Synthesis". ATVA 2015: 394-410 (url, free access)

- Rüdiger Ehlers, Robert Könighofer, Roderick Bloem (TU Graz), "Synthesizing cooperative reactive mission plans". IROS 2015, pp. 3478-3485 (url, free access)

- Roderick Bloem, Daniel M. Hein, Franz Röck, Richard Schumi (TU Graz), "Case Study: Automatic Test Case Generation for a Secure Cache Implementation", TAP 2015, pp. 58-75 (url)

Presentations and Invited Talks

2017

- (Keynote talk) A. Jutman (TL), “How not to screw up the board/system test with a bad IC-level DFT” Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ’2017), Lübeck, Germany, March 5-7, 2017

- (Invited talk) Heinz Riener (DLR), "CEGAR-based EF Synthesis of Boolean functions with an Application to Circuit Rectification", Centre SI Seminar at EPFL, February 2, 2017, Lausanne, Switzerland, http://si.epfl.ch/page-141443-en.html

2016

- (Keynote talk) Jaan Raik (TUT),  "Towards Cost-effective, Resilient Many-core Architectures" at the ECSI DASIP 2016 Conference on Design & Architectures for Signal & Image Processing, October 12-14, 2016, Rennes, France (event).

- (Keynote talk) Artur Jutman (TL), "From reliability to SoC-level fault management", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), VLSI-SoC 2016, September 26-28, 2016 (event).

- (Keynote talk) A. Jutman, “How not to screw up the board/system test with a bad IC-level DFT” Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ’2017), Lübeck, Germany, March 5-7, 2017.

- Special Session on "Designing Reliable Cyber-Physical Systems" organised at the Forum on specification & Design Languages (FDL'16) in Bremen, Germany, September 14-16, 2016.
Presentations:
  • Hans G. Kerkhoff (University of Twente) "Health Monitoring of CPS"
  • Konstantin Shibin (Testonica Lab) "Managing Faults at SoC Level During In-Field Operation of CPS"
  • Gerard Rauwerda (Recore Systems) "Many-Core Resource Management for Fault Tolerance"
  • Shiri Moran (IBM Research Lab) "Comprehensive and Scalable RT-level Reliability Analysis"
- (Invited talk) A. Jutman, K. Shibin, S. Devadze, M. Grabmann, R. Pricken (TL), “Managing Faults in Many-Core Systems During Operation”, 11th Int. Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC’2016), Tallinn, Estonia June 27-29, 2016.

- (Panelist) Jaan Raik (TUT),  August 25, 2016, Rome, Italy. IMMORTAL was presented at the panel "Panel on Systems Reliability, Topic: Challenges and Common Industrial Practice to Improve Systems Reliability" of the VALID'16 conference (event).

- (Panel Organizer) Jaan Raik (TUT), (Panelist) Artur Jutman (TL) Panel Session: “Quo Vadis High-Level Test?”, IEEE Workshop of RTL and High-Level Testing – WRTLT’16, November 24-25, 2016, Hiroshima, Japan.

- (Presentation) Heinz Riener (DLR), "Immortalizing Many-Core Based Cyber-Physical Systems", ARTEMIS Spring Event 2016, 13-14 April 2016, Vienna, Austria (event, pdf)

- (Invited Talk) Gerard Rauwerda (Recore Systems), "Many-core processor architectures; fault-tolerance and programmability", 4th Workshop on High-performance and Real-time Embedded Systems (HiRES'16) at HiPEAC 2016, 19 January 2016, Prague, Czech Republic (event)

- (Invited Talk) Gerard Rauwerda (Recore Systems), "Multi-/many-core Embedded Systems - Parallel programming, run-time mapping and fault-tolerance", Workshop Software Engineering; Programming Future Large Scale IT Systems at HiPEAC 2016, 19 January 2016, Prague, Czech Republic (event)

- (Embedded tutorial) A. Jutman E. Larsson (TL), “In-Field System-Health Monitoring based on IEEE 1687” 1st Int. Test Standards Application Workshop (TESTA’2016), Amsterdam, The Netherlands, May 26-27, 2016.

2nd IMMORTAL Dissemination Workshop at IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), VLSI-SoC 2016, September 28-29, 2016, Tallinn, Estonia. (event)

- Kim Sunesen, Gerard Rauwerda (RS), Hans Kerkhoff (UT) "Highly dependable many-core SoCs by lifetime prediction and embedded instrumentation"

- Eli Arbel, Shiri Moran (IBM), Roderick Bloem, Franz Röck (TUG), Jaan Raik, Ranganathan Hariharan (TUT), "Advances in checker verification"

- Heinz Riener, Jan Malburg, Görschwin Fey (DLR), "Tool Support for Design Understanding"

 

2015

IMMORTAL at the MEDIAN Finale Event, November 11, 2015, Tallinn, Estonia. (event)
Talks:
  - Jaan Raik (Tallinn UT), "Immortalizing Many-Core Based Cyber-Physical Systems"
  - Gerard Rauwerda (Recore Systems), "Many-Core SoC Architectures: Run-Time Mapping and Fault Tolerance"
  - Yong Zhao (U.Twente), "Design-for-Raliability in MP-SoC via Health Monitoring"
  - Konstantin Shibin (Testonica Lab), "Fault Management Using IJTAG Instrument Networks"

- Shiri Moran (IBM), "Meeting the RAS verification challenge: IBM's perspective on verifying design reliability", the 16th International Workshop on Microprocessor and SOC Test and Verification in Austin (MTV 2015) (event)

- (Guest lecture at U.Twente) Gerard Rauwerda (Recore Systems), "Many-core Embedded Systems", Enschede, NL, 23 November 2015

- (Guest lecture at U.Twente) Timon ter Braak (Recore Systems), "Run-time Mapping", Enschede, NL, 30 November 2015

- (Invited Talk) Jaan Raik (Tallinn UT), "Immortalizing Many-Core Systems: Early Experiences of the Horizon 2020 Action IMMORTAL", at the 7th International Workshop on Dependable Many-Core Computing (DMCC) in Amsterdam, July 23, 2015 (event)

- A. Jutman (Testonica Lab), “IEEE 1687 Monitoring Infrastructure for Aging Failure Management”, 1st  International Workshop on Reliability and Aging in Forthcoming Electronic Systems (RAFES @ ETS’2015), Cluj-Napoca, Romania, May 28-29, 2015 (event)

- Franz Röck (TU Graz), "Case Study: Automatic Test Case Generation for a Secure Cache Implementation", at TAP 2015, July 22, 2015 in L'Aquila, Italy (event)

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