This project has received funding from the EUís Horizon 2020 programme for research, technological development and demonstration under grant agreement no 644905.

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IMMORTAL ASIC Implementation Completed

As a cooperation between Tallinn University of Technology, University of Twente, Testonica Lab and Recore Systems, IMMORTAL demo ASIC has been implemented in 40nm TSMC technology and submitted for manufacturing into IMEC, Leuven, Belgium. The ASIC consists in fact of two chips, a fault-resilient quad-core design with embedded concurrent error checkers and monitors, as well as a chip with test instruments of voltafe, IDDT, slack and temperature monitors.

09.04.2018

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